This invention relates to programmable logic devices, and more particularly to the manner in which the regions of programmable logic on such devices are organized and interconnected.
Many current programmable logic integrated circuit devices have a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Examples of such devices are shown in Pedersen et al. U.S. Pat. No. 5,260,610, Cliff et al. U.S. Pat. No. 5,260,611, Cliff et al. U.S. patent application Ser. No. 08/442,795, filed May 17, 1995, and Cliff et al. U.S. patent application Ser. No. 08/672,676, filed Jun. 28, 1996, all of which are hereby incorporated by reference herein. In such devices horizontal interconnection conductors may be associated with each row of regions for conveying signals to, from, and between the regions in that row. Vertical interconnection connection conductors may be associated with each column of regions for conveying signals to, from, and between the rows.
There are demands for programmable logic devices with more and more programmable logic regions. It may not be desirable, however, to provide more logic regions by simply increasing the number of logic regions in each row and/or increasing the number of rows. This is so because this expedient increases the number of programmable connections to and/or from the horizontal and/or vertical conductors. The loading on these conductors may therefore become undesirably large and signal propagation speed along them undesirably slow. The large number of programmable connections to the horizontal and/or vertical conductors also requires a correspondingly large number of programmable memory elements for controlling those connections. These numerous programmable connections and associated memory elements may result in an inefficient use of silicon area.
In view of the foregoing, it is an object of this invention to provide improved organizations for the logic regions and interconnection conductors of programmable logic devices.
It is a more particular object of this invention to provide organizations for programmable logic devices which allow the number of regions on the device to be greatly increased without excessively increasing the loading on any one type of interconnection conductor.